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Altera_Forum
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16 years ago

Recovery - DCFIFO issue

Hi, I have a design where a block of logic writes data to a DCFIFO at 66MHz and a seperate block reads the FIFO at 0.576MHz and sends the data through a RS232 interface. Also received data from th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Thanks avemo for the reponse.

I placed the cosntraints that you suggested instead of the ones I had in place cutting the paths between both clocks, but it gave me the same warnings as before with the recovery.

From reading the link you provided, I understand that the registers in the constraint are the internal registers of the FIFO? I don´t understand what the terms specifically refer to. for example what does rdptr_g and the others specifically refer to?

Anyway it seems that this constraint is nessesery and should be in my .sdc file. Any other information regarding other contraints nessesery to solve the recovery issue would be most welcome.

Many Thanks