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Altera_Forum's avatar
Altera_Forum
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12 years ago

Recompilation after modifications in signaltap

Hello everybody, I'm facing a long compilation times issue in Quartus everytime I make any modifications in the signal set (i have a Nios II + custom coprocessor system which takes more than 1 ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Since SignalTap has to re-routing the FPGA, It is hard to compile partitions only.

Since Signaltap needs a compile, so as the FPGA to be configured, ignoring signals afterwards will not optimize the FPGA ressources.

For a work around, as i said, you can set a wide range of significant signals,

You can change your signaltap clock to a slower "clock"

You can use transitional storage

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