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Altera_Forum's avatar
Altera_Forum
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12 years ago

Reading and Writing Text File in VHDL

Hi guys. I have tried run this coding. But, it has error. Why it happens? Btw, i refer to this website for the tutorial. http://vhdlguru.blogspot.com/2010/03/reading-and-writing-files-in-vhd...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Simulation allows you to test the code you want to deploy

Synthesis converts your code to hardware blocks. So for FPGAs it maps your code to the base level LUTs, registers, memories, multipliers etc.