Read responses on not reaching PIO interface through mm_interconnect

Question

Hi,
Quartus Version : 22.2.0.94
A "Multi Channel DMA Intel® FPGA IP for PCI Express" IP is integrated with AXI4 DUT and On Chip Memory.

Data Responses for BAR2 MMIO read requests are not reaching PIO interface.
The attached "NoReadResponseAtPIO.png" shows
=&gt; a valid Read response is present on DUT AXI interface.
=&gt; rx_pio_waitrequest_i goes low
=&gt; rx_pio_readdatavalid_i does not toggle.

This results in a hang in mm_interconnect. Subsequent read/writes initiated on rx_pio does not pass through mm_interconnect.

How can we overcome this issue?

Regards
Siva Kona

wincent_altera · Answer

Hi,The PIO is always mapped to BAR2, see 3.1.4. Avalon-MM PIO Master:https://www.intel.com/content/www/us/en/programmable/documentation/xzr1589413426034.html#pis1593481713202See also 4.1.1 which mentions the addressing:https://www.intel.com/content/www/us/en/programmable/documentation/xzr1589413426034.html#yxs1589416421751BAR0 is always used for the Control Register Block (CSR), see 3.1.9. Control Registershttps://www.intel.com/content/www/us/en/programmable/documentation/xzr1589413426034.html#obt1591741708879The Bursting Avalon-MM Master (BAM) can be mapped to any BAR other than 0, see 3.2. Bursting Avalon-MM Master (BAM)https://www.intel.com/content/www/us/en/programmable/documentation/xzr1589413426034.html#jtr16200841363178.2.7 API List, table 97 to 100 detail the PIO API format:https://www.intel.com/content/www/us/en/programmable/documentation/xzr1589413426034.html#wqx1626225113388Our Example Design can be generate to include a PIO Master on BAR2, as a starting point you may want to generate and refer to that:https://www.intel.com/content/www/us/en/programmable/documentation/nki1590181067003.html#bdn1621555193678Regards,Wincent_Intel

sivakona · Answer

Hi Wincent_Intel, Good Morning!

We have generated an SOF with Quartus Version 22.3 and observed the same behavior to persist. 
The issue is NOT resolved yet. Request you for further inputs.

Is this behavior due to issues in mm_interconnect or PCIe Endpoint?

Regards
Siva Kona

wincent_altera · Answer

Will close here as the communication move to private.

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Read responses on not reaching PIO interface through mm_interconnect

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