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SivaKona's avatar
SivaKona
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Read responses on not reaching PIO interface through mm_interconnect

Hi, Quartus Version : 22.2.0.94 A "Multi Channel DMA Intel® FPGA IP for PCI Express" IP is integrated with AXI4 DUT and On Chip Memory. Data Responses for BAR2 MMIO read requests are not reach...
Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,


The PIO is always mapped to BAR2, see 3.1.4. Avalon-MM PIO Master:

https://www.intel.com/content/www/us/en/programmable/documentation/xzr1589413426034.html#pis1593481713202

See also 4.1.1 which mentions the addressing:

https://www.intel.com/content/www/us/en/programmable/documentation/xzr1589413426034.html#yxs1589416421751


BAR0 is always used for the Control Register Block (CSR), see 3.1.9. Control Registers

https://www.intel.com/content/www/us/en/programmable/documentation/xzr1589413426034.html#obt1591741708879


The Bursting Avalon-MM Master (BAM) can be mapped to any BAR other than 0, see 3.2. Bursting Avalon-MM Master (BAM)

https://www.intel.com/content/www/us/en/programmable/documentation/xzr1589413426034.html#jtr1620084136317


8.2.7 API List, table 97 to 100 detail the PIO API format:

https://www.intel.com/content/www/us/en/programmable/documentation/xzr1589413426034.html#wqx1626225113388


Our Example Design can be generate to include a PIO Master on BAR2, as a starting point you may want to generate and refer to that:

https://www.intel.com/content/www/us/en/programmable/documentation/nki1590181067003.html#bdn1621555193678


Regards,

Wincent_Intel