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SivaKona's avatar
SivaKona
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Read responses on not reaching PIO interface through mm_interconnect

Hi, Quartus Version : 22.2.0.94 A "Multi Channel DMA Intel® FPGA IP for PCI Express" IP is integrated with AXI4 DUT and On Chip Memory. Data Responses for BAR2 MMIO read requests are not reach...
SivaKona's avatar
SivaKona
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Hi Wincent_Intel, Good Morning!

We have generated an SOF with Quartus Version 22.3 and observed the same behavior to persist.

The issue is NOT resolved yet. Request you for further inputs.

Is this behavior due to issues in mm_interconnect or PCIe Endpoint?

Regards

Siva Kona