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Altera_Forum's avatar
Altera_Forum
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8 years ago

Read in external ADC values

Hello everybody,

I'm a newbie on VHDL programming, but for a course at university we have to deal with the DE1-SoC and the THDB-ADA Board.

I want to read out the values of the ADC and display them in the signal analyzer in Quartus.

So this is my source code (.vhdl):

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity adc_test is

port(

adc_cs_n: in std_logic; --internal adc

adc_din: out std_logic;

adc_dout: in std_logic;

adc_sclk: out std_logic;

clock_50: in std_logic; --clocks

clock2_50: in std_logic;

clock3_50: in std_logic;

clock4_50: in std_logic;

dram_addr: out std_logic_vector(12 downto 0); --sdram

dram_ba: out std_logic_vector(1 downto 0);

dram_cas_n: out std_logic;

dram_cke: out std_logic;

dram_clk: out std_logic;

dram_cs_n: out std_logic;

dram_dq: inout std_logic_vector(15 downto 0);

dram_ldqm: out std_logic;

dram_ras_n:out std_logic;

dram_udqm: out std_logic;

dram_we_n: out std_logic;

adc_clk_a: out std_logic; --gpio

adc_clk_b: out std_logic;

adc_da: in std_logic_vector(13 downto 0);

adc_db: in std_logic_vector(13 downto 0);

adc_oeb_a:out std_logic;

adc_oeb_b:out std_logic;

adc_otr_a:in std_logic;

adc_otr_b:in std_logic;

dac_clk_a: out std_logic;

dac_clk_b: out std_logic;

dac_da: in std_logic_vector(13 downto 0);

dac_db: in std_logic_vector(13 downto 0);

dac_mode: out std_logic;

dac_wrt_a: out std_logic;

dac_wrt_b: out std_logic;

osc_sma_adc4: in std_logic;

power_on: out std_logic;

sma_dac4: in std_logic

);

end adc_test;

architecture arch_adc of adc_test is

signal clk : std_logic;

begin

process(clock_50)

begin

clk <= clock_50;

end process;

end arch_adc;

Complilation succeeded but when I start the signal analyzer it displays "waiting for clock".

Do you have some ideas what I forgot to include?

Do I have to include an pll?

Thank you for your help.

Christoph :o

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    --- Quote Start ---

    Hi,

    can you post your SignalTap setup window?

    --- Quote End ---

    hi vlrean,

    I solved this problem already, i forgot to map the clock_50 on the right hand side of the window (signal configuration).

    But I didn't see any signal input.

    Best regards,

    Chris
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    Are ADC_CLK_A and ADC_CLK_B clocks to the ADC? If so, you don't appear to be driving them (of course, it's a bad idea to clock an ADC from an FPGA output). Are ADC_OEB_A and ADC_OEB_B enables for the ADC? Make sure the ADC is not powered down. You don't say how you are triggering SignalTap. Some boards have lots of jumpers that must be set.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    --- Quote Start ---

    Are ADC_CLK_A and ADC_CLK_B clocks to the ADC? If so, you don't appear to be driving them (of course, it's a bad idea to clock an ADC from an FPGA output). Are ADC_OEB_A and ADC_OEB_B enables for the ADC? Make sure the ADC is not powered down. You don't say how you are triggering SignalTap. Some boards have lots of jumpers that must be set.

    --- Quote End ---

    hi corestar,

    thank you for your suggestion, but I solved the problem.

    my updated code is:

    library ieee;

    use ieee.std_logic_1164.ALL;

    use ieee.std_logic_unsigned.all;

    entity ADC_test is

    port(

    ADC_CS_N: in std_logic; --internal ADC

    ADC_DIN: out std_logic;

    ADC_DOUT: in std_logic;

    ADC_SCLK: out std_logic;

    CLOCK_50: in std_logic; --clocks

    CLOCK2_50: in std_logic;

    CLOCK3_50: in std_logic;

    CLOCK4_50: in std_logic;

    DRAM_ADDR: out std_logic_vector(12 downto 0); --SDRAM

    DRAM_BA: out std_logic_vector(1 downto 0);

    DRAM_CAS_N: out std_logic;

    DRAM_CKE: out std_logic;

    DRAM_CLK: out std_logic;

    DRAM_CS_N: out std_logic;

    DRAM_DQ: inout std_logic_vector(15 downto 0);

    DRAM_LDQM: out std_logic;

    DRAM_RAS_N:out std_logic;

    DRAM_UDQM: out std_logic;

    DRAM_WE_N: out std_logic;

    ADC_CLK_A: out std_logic; --GPIO

    ADC_CLK_B: out std_logic;

    ADC_DA: in std_logic_vector(13 downto 0);

    ADC_DB: in std_logic_vector(13 downto 0);

    ADC_OEB_A:out std_logic;

    ADC_OEB_B:out std_logic;

    ADC_OTR_A:in std_logic;

    ADC_OTR_B:in std_logic;

    DAC_CLK_A: out std_logic;

    DAC_CLK_B: out std_logic;

    DAC_DA: in std_logic_vector(13 downto 0);

    DAC_DB: in std_logic_vector(13 downto 0);

    DAC_MODE: out std_logic;

    DAC_WRT_A: out std_logic;

    DAC_WRT_B: out std_logic;

    OSC_SMA_ADC4: in std_logic;

    POWER_ON: out std_logic;

    SMA_DAC4: in std_logic

    );

    end ADC_test;

    architecture arch_adc of ADC_test is

    begin

    DAC_MODE <= '0';

    ADC_CLK_B <= CLOCK_50;

    ADC_CLK_A <= CLOCK_50;

    ADC_OEB_A <= '0';

    ADC_OEB_B <= '0';

    POWER_ON <= '1';

    end arch_adc;

    My current question is how to integrate the PLL from the Megawizard of the Quartus software.

    Best regards,

    Chris