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Are ADC_CLK_A and ADC_CLK_B clocks to the ADC? If so, you don't appear to be driving them (of course, it's a bad idea to clock an ADC from an FPGA output). Are ADC_OEB_A and ADC_OEB_B enables for the ADC? Make sure the ADC is not powered down. You don't say how you are triggering SignalTap. Some boards have lots of jumpers that must be set.
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hi corestar,
thank you for your suggestion, but I solved the problem.
my updated code is:
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
entity ADC_test is
port(
ADC_CS_N: in std_logic; --internal ADC
ADC_DIN: out std_logic;
ADC_DOUT: in std_logic;
ADC_SCLK: out std_logic;
CLOCK_50: in std_logic; --clocks
CLOCK2_50: in std_logic;
CLOCK3_50: in std_logic;
CLOCK4_50: in std_logic;
DRAM_ADDR: out std_logic_vector(12 downto 0); --SDRAM
DRAM_BA: out std_logic_vector(1 downto 0);
DRAM_CAS_N: out std_logic;
DRAM_CKE: out std_logic;
DRAM_CLK: out std_logic;
DRAM_CS_N: out std_logic;
DRAM_DQ: inout std_logic_vector(15 downto 0);
DRAM_LDQM: out std_logic;
DRAM_RAS_N:out std_logic;
DRAM_UDQM: out std_logic;
DRAM_WE_N: out std_logic;
ADC_CLK_A: out std_logic; --GPIO
ADC_CLK_B: out std_logic;
ADC_DA: in std_logic_vector(13 downto 0);
ADC_DB: in std_logic_vector(13 downto 0);
ADC_OEB_A:out std_logic;
ADC_OEB_B:out std_logic;
ADC_OTR_A:in std_logic;
ADC_OTR_B:in std_logic;
DAC_CLK_A: out std_logic;
DAC_CLK_B: out std_logic;
DAC_DA: in std_logic_vector(13 downto 0);
DAC_DB: in std_logic_vector(13 downto 0);
DAC_MODE: out std_logic;
DAC_WRT_A: out std_logic;
DAC_WRT_B: out std_logic;
OSC_SMA_ADC4: in std_logic;
POWER_ON: out std_logic;
SMA_DAC4: in std_logic
);
end ADC_test;
architecture arch_adc of ADC_test is
begin
DAC_MODE <= '0';
ADC_CLK_B <= CLOCK_50;
ADC_CLK_A <= CLOCK_50;
ADC_OEB_A <= '0';
ADC_OEB_B <= '0';
POWER_ON <= '1';
end arch_adc;
My current question is how to integrate the PLL from the Megawizard of the Quartus software.
Best regards,
Chris
Honored Contributor
