I notice several things wrong with your VHDL - I've made the comments next to the lines of code:
library std;
library ieee;
use std.textio.all;
use ieee.std_logic_1164.all;
There is also the package ieee.std_logic_textio that allows you to read/write directly to std_logic(vectors). It has OREAD and HREAD functions too, allowing you to read octal and hex strings.
process(clock)
variable inline:line;
variable character_variable:character;
variable end_of_line:boolean;
file myfile:text is "cod.txt";
I recommend using the '93 file handling:
file : myfile : text open READ_MODE is "cod.txt";
readline(myfile,inline);
read(inline,character_variable,end_of_line);
for i in 0 to 7 loop
read(inline,character_variable,end_of_line);
case character_variable is
when '0' =>
output <= '0';
when '1' =>
output <= '1';
when others =>
output <= 'Z';
end case;
end loop;
The reason you are getting 'Z' is that when you get a rising edge of the clock, it is reading all 8 characters in the same delta cycle, so time doesnt actually advance until it's finished the file. What you need to do is wait after each character read.
What is the end_of_line variable for?
if you use std_logic_texio, theres no need for reading characters, you can read directly into the output. Also, as you dont need it to be synthesisable, you can do whatever you want with regards wait statements and other useful stuff:
process --note no clock - this is important cos you need to use wait statements
file myfile : text;
variable inline : line;
begin
FILE_OPEN(myfile, "cod.txt", read_mode);
readline(myfile, inline);
for i in 0 to 7 loop
read(inline, output);
wait until rising_edge(clk);
end loop;
FILE_CLOSE(myfile); --so we can restart the file
end process;