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James_B
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4 years ago

Quartus allows redundant overloaded functions in VHDL without a compiler error ??

I have a question on why does Quartus allow redundant overloaded functions to be compiled without raising an error condition. An example overloaded illegal redeclaration in a VHDL package is shown...
James_B's avatar
James_B
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4 years ago

Nurina, The basic_data_types.vhd file is included in github now.

The design takes approximately 10 minutes to compile.

Also, if you want to see the uart readout, you need to add a small FTDI usb uart to the gpio pins GPIO_9 (Rx) and GPIO_11 (Tx)

Thanks, James