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Subhabrata's avatar
Subhabrata
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3 years ago
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Platform Designer Nios HDL generation

I have created NIOS II based system in Platform Designer (Quartus Prime Lite 18.1). completed all connection, memory mapping and IRQ. But to generate HDL (Generate -> generate HDL), I am getting on...
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  • RichardT_altera's avatar
    RichardT_altera
    3 years ago

    If you look into the project directory -> ip -> {example_ip_name} -> synth folder, that's where the top level vhdl file generated for that particular IP, used in your qsys system.

    example file path: .../<project directory>/ip/<example_ip_name>/synth

    You can find it at the top level qsys synth folder as well, go to project directory -> {top_qsys_name} -> synth.

    example file path: .../<project directory>/<top_qsys>/synth


    The other generated file with sub-system component are usually generated in .v or .sv files format.

    example file path with sub-system/ip:

    .../<project directory>/ip/<example_ip_name>/<sub-system>/synth

    .../<project directory>/<top_qsys>/<example_ip_name>/synth


    Best Regards,

    Richard Tan

    p/s: If you find any answers from the community or Intel Support to be helpful, we encourage you to mark them as the best answer or rate them 4/5 in the survey.


robinr's avatar
robinr
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3 years ago

If i got this correct (can someone verify?) when i talked with people from mathworks, there is no problem with mixed verilog and vhdl when creating a design and programing your target with, but it can (could?) be a problem when doing simulation. And people working on fixing that solution just happend to generate verilog code from simulink and it just became the way for solving the problem, and it has become a sort of non-problem. but i asked them this very question when i met them during my education.