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GOMEZ_IT's avatar
GOMEZ_IT
Icon for Occasional Contributor rankOccasional Contributor
26 days ago
Solved

CYCLONE IVE ODDR delay mismatch

Hello Altera Experts! I am using Quartus Standard 24.1.. I'm building a 10-bit parallel output interface to drive a DAC. I'm using the oddr (ALTDDIO_OUT) registers so that all bits output simultane...
Timing
  • ShengN_altera's avatar
    ShengN_altera
    17 days ago

    The routing delay difference due to different type of pin assigned.

    The bit fpga_dac_CHA[3] using this type of pin:

     

     

    While other bits using these type of pin:

     

     

    Different pin type will have different internal routing delay and this is fix one which cannot be changed.

    So if change bit fpga_dac_CHA[3] and fpga_dac_CHB[3] pins to for example PIN_115 and PIN_120. The timing will be similar for all bits:

     

GOMEZ_IT's avatar
GOMEZ_IT
Icon for Occasional Contributor rankOccasional Contributor
12 days ago

I'm still unsure about the false path issue. I can't figure out why I should disable the path between the falling edge of launch-clk and the rise edge of latch-clk. The launch-clk for oddrs could also be the falling one, since it's a ddr.