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Altera_Forum
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15 years ago

ram with byte enable

Is it possible to infer a block ram with byte enable in VHDL using Quartus II? I'm trying to infer a 1024x32 single port ram with 4 enable bits, but after synthesis, Quartus II infers 4 independient ...
Altera_Forum's avatar
Altera_Forum
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15 years ago

Sorry no way to do that.

You need to use two VHDL architecures, one for altera direct instantiation and one for Xilinx direct instantiation.

I have experience with both and this is the only way I think it will work.

Inferrence of byte enables is not supported by Altera nor Xilinx