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New ContributorRAM inference not working for initialized RAM
According to documentation RAM initialization should work in VHDL by simply adding an initialization value to the memory array.
However, In my code (see attached), this is not the case. Without initialization value (resp. with initializing all content to zero) the code infers 8kb RAM - so the syntax seems fine for RAM inference. As soon as I add any other initialization content than zeros, registers are inferred (not RAM).
I have attached my code containing both cases.
With line 109 uncommented, RAM inferrence works:
With line 108 uncommented, RAM inferrence fails:
signal Mem_v : Data_t(Depth_g - 1 downto 0) := (0 => x"1234", 1 => x"5678", others => (others => '0'));
Why is RAM inference not working? What can I do to make it work?
18 Replies
ShengN_alteraSuper Contributor
Hi,
I had open an enhancement request to internal team for Standard version.
For license, you can generate the evaluation license from SSLC https://licensing.intel.com/psg/s/?language=en_US, usually evaluation license is used to evaluate the Quartus Tool.
Thanks,
Regards,
Sheng
JoEobruendl: I had a similar problem today. In my design, multiple DPRAMs are instatiated using a "for ... generate" loop, similar to your example.
Without initialization, the memories are inferred in RAM, but when i add an initialization function, only the MSB of these memories gets infered and the rest is implemented as registers.
Modifying the code as suggested above is not a solution for me, because the number of memories depends on a generic in my design, so i need the generate loop.
Then i found a solution: I added a separate entity for the DPRAM, including the initialization function and instantiated the DPRAM as component multiple times in the "for ... generate" loop. With this modification all memory bits were inferred in RAM without any problem.
Maybe this could also be a solution for your project.
- ShengN_altera
Sorry for late reply. The enhancemnet request had been rejected by internal team
