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obruendl's avatar
obruendl
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9 months ago

RAM inference not working for initialized RAM

According to documentation RAM initialization should work in VHDL by simply adding an initialization value to the memory array. https://www.intel.com/content/www/us/en/docs/programmable/683082/21-3/...
Hdl
ShengN_altera's avatar
ShengN_altera
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9 months ago

Hi,


You may try with the pro version. The pro version has 30-day evaluation license.


Btw, I had done the testing in pro version and it works well.


Thanks,

Regards,

Sheng


FvM's avatar
FvM
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9 months ago
Hi,
despite of license requirements, Pro version is not a solution because you don't have a choice to use either Std/Lite or Pro version for a specific FPGA series.
Although I'm frequently using RAM inference in my code, with both Quartus versions, I must confess that I'm surprised about the observed behaviour. Curiously Quartus infers RAM for 1 bit and registers for the other 15 bits of 16 Bit word in the present example. In fact the problem doesn't occur with Altera suggested RAM coding style.
    • FvM's avatar
      FvM
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      9 months ago
      Hi ShengN,
      thanks for the links. Apparently I didn't yet infer Byte Enable with Quartus Standard. It's strange though that generated byte enable doesn't work, even with true generate for statement. But we should take it as is.
      • obruendl's avatar
        obruendl
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        9 months ago

        I have to be honest - I disagree with the conclusion "we should take it as it is".

        The situation as I understood is:
        - No tool supports all FPGA series (some are exclusively for lite, some exclusively for pro)
        - The two tool versions have different coding requirements for inference (its not "pro just understands more")

        If this is true, this would mean no-one can write code that compiles for all Altera devices. Which is rather catastrophic - how would people provide IP for your devices. My library is open-source - but there also is the whole business of paid IP. And all IP actually acts as enabler for Altera devices being used in applications. Why would Altera put stones into the way of people producing IP for their devices? And why would Altera want to put itself in a far much less customer friendly position than its competitors that provide the exact same synthesis engine in paid and free versions (and just differ in terms of IP, device support and the like)?

        My vote here would rather be pushing towards fixing the situation.

        Way Forward

        I still would hope that I can at least find a way to write modular inference based code at least with the Pro version (the restrictions of Standard make this impossible). Using a eval version is not an option - I am aiming for long term maintenance. Please check if there is a way to get a free Pro license for Open Logic (an open source project acting as enabler for customers using your devices).

        I'd prefer documenting that with Pro version (even if this restricts the target devices) everything works fine over stating that there are severe limitations for Altera. But finally the choice to provide a license or not is Alteras.