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obruendl's avatar
obruendl
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9 months ago

RAM inference not working for initialized RAM

According to documentation RAM initialization should work in VHDL by simply adding an initialization value to the memory array. https://www.intel.com/content/www/us/en/docs/programmable/683082/21-3/...
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obruendl's avatar
obruendl
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9 months ago

I have even more interesting news. I fixed my memory to 16 bits and played with the exact formulations in VHDL.

Below code fails to infer RAM:

for byte in 0 to 1 loop
    if Wr_Be(byte) = '1' then
        Mem_v(to_integer(unsigned(Wr_Addr)))(byte * 8 + 7 downto byte *  := Wr_Data(byte * 8 + 7 downto byte * 8);
    end if;
end loop;

If I just unroll the loop, RAM is inferred correctly:

if Wr_Be(0) = '1' then
    Mem_v(to_integer(unsigned(Wr_Addr)))(7 downto 0) := Wr_Data(7 downto 0);
end if;
if Wr_Be(1) = '1' then
    Mem_v(to_integer(unsigned(Wr_Addr)))(15 downto  := Wr_Data(15 downto 8);
end if;

I feel like formulating the very same thing in a loop or unrolled should lead to the same results and if it does not, I'd call this a bug.


Unfortunately I still didn't find a language construct to cleanly work around this bug for parametrizable code - without understanding the root-cause making Quartus to behave different for the two snippets above it is difficult to find one because this (to my understanding) is not a logical issue.

Please provide suggestions how this issue can be worked around. Alternatively I could accept a confirmation of this being a bug that will be fixed in the next release of Quartus. If I know its getting fixed it'd be fine for me to just document that RAM inference for Altera works correctly starting from 25.1.