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obruendl's avatar
obruendl
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9 months ago

RAM inference not working for initialized RAM

According to documentation RAM initialization should work in VHDL by simply adding an initialization value to the memory array. https://www.intel.com/content/www/us/en/docs/programmable/683082/21-3/...
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obruendl's avatar
obruendl
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9 months ago

The code describes a simple-dual-port memory of 4kbit in size. Yes, some RAM is inferred but in addition to that RAM I see > 7000 registers which I would not be expected. The code really only describes a RAM.

In the meantime a contributor of Open Logic identified that RAM inference works correctly when commenting out the Byte-Enable Logic. See GitHub issue for details: https://github.com/open-logic/open-logic/issues/122

The strange thing is that the configuration of the RAM I use here does not even make use of Byte Enables. Generics are set to not use Byte-Enables - so the logic that breaks inference is unused.

I agree that the files I provided are inconsistent because I tried out a few things. I now archived the project in Quartus (QAR) in two ways:
- The failing version (including byte-enable logic): https://drive.google.com/file/d/13sTr6c7nqkbVoqz2a4C808FaXzsyirUN/view?usp=drive_link

- A version with byte-enable logic commented (which does infer RAMs correctly): https://drive.google.com/file/d/10Wbemcy09Xk6Y99eESxcZIhgwJy5aTuf/view?usp=drive_link