--- Quote Start ---
Hi again,
I didn´t have quartus updated with SP2. I am currently downloading it and will report back on whether things improve.
When I generate the .qxp file I generate a post synthesis netlist. I didn´t generate a post fitting netlist as the othe rteam have to put their part of the design on the FPGA and I wanted to leave things more flexible. Should I have used a post fitting netlist? Would this improve things and why?
Thansk again for the help.
--- Quote End ---
Hi,
in your case is the synthesis netlist the right choice, as long as you don't need e.g. placement for preserving the timing. In your first post you mentioned that some of
your "create_clock" assignment are ignored. Can tell a little more about this issue ?
Kind regards
GPK
Honored Contributor
