Hi pletz,
Thanks for the reply. I am not generating clocks inside the imported components. All clocks enter via the device pins and there is a pll in the top level which also genterates a clock.
In my top level project, I may have incorrectly defined the components as design partitions. I right clicked on the component in hierarchy window and and clicked set as design partition. I was unsure as to how to do this, so what I did was instantiate the component while the vhdl files or .qxp files was not included in the project, then ran synthises, it produced an error, and then was able to right click it. Without doing this the component didn´t show up in the hierarchy window. I am sure there must be a better way to do this.
I am successfully able to instantiate one component this way, but when I add the 2nd, when it does the timing analysis, quartus produces a fatal error and stops. i would be very gratful if you could tell me what i am doing wrong.
Thanks again