Qurtus vs Modelsim

The "inferring latch(es)" warning is given, because for some cases/input conditions no value is assigned to the signals. The compiler

adds a logic loop to hold the previous state in this cases. You should consider, what's the actual intended logic behaviour. Adding

Next_State <= Present_State; in front of the case construct is one way to cancel the logic loop, a complete decoding for Next_State another.

I don't see, why a warning is given for signal "done", although I wonder, if the "onw-way" assignment is achieving the intended purpose.

Generally, feeding done to the state machine without synchronzing it to clk before can cause timing violations and unexpected behaviour.

Finally in the below code, clk_r <= '1' is simply ignored:

  elsif (rising_edge(clk20khz)) then
    clk_r <= '1';
    clk_r <= not clk_r;
  end if;