Qurtus vs Modelsim

To be synthesizable, sequential processes must follow the basic scheme shown in the Quartus VHDL templates

process(reset, clk) is 
-- Declaration(s) 
  begin 
    if(reset = '1') then
      -- Asynchronous Sequential Statement(s) 
    elsif(rising_edge(clk)) then
      -- Synchronous Sequential Statement(s)
    end if;
  end process;

Edge sensitive expressions inside of a combinational process can't be represented in hardware. If you need e.g. to start a timer from the combinational process, place it in an individual process and make it act on the state variables.