Qurtus vs Modelsim

OK, THX, Now I use process to detect edge in signal done_ps2 and Quartus accepted this structure, but in other file i detect 2 edge in one clock. How else solve this probelm?

--registers
    process (clk20khz, rst)
    begin
        if rst = '0' then
            Present_State <= ST_idle;
            c_reg <= (others => '0');
            b_reg <= (others => '0');
            n_reg <= (others => '0');
        elsif (clk20khz'event and clk20khz ='1') then
            Present_State <= Next_State;
            c_reg <= c_next;
            b_reg <= b_next;
            n_reg <= n_next;
        end if;
    end process;
--odd parity bit
    par <= not (dane_we(7) xor dane_we(6) xor dane_we(5) xor dane_we(4) xor
                dane_we(3) xor dane_we(2) xor dane_we(1) xor dane_we(0));
-----------------------------------------------------------------------------
    process(Present_State, n_reg, b_reg, c_reg, dane_we, par, fall_edge, start, clk20khz)
    begin
    ---Next_State <= Present_State;
    c_next <= c_reg;
    n_next <= n_reg;
    b_next <= b_reg;
    
    ps2c_out <= '1';
    ps2d_out <= '1';
    tri_c <= '0';
    tri_d <= '0';
    
    
    
    
    case Present_State is
        when ST_idle =>
          done <= '0';
            if start = '1' then
                b_next <= par & dane_we;
                c_next <= "0000010";        -- wait 100 us  
                Next_State <= ST_rts;
            else
                Next_State <= ST_idle;
            end if;
        when ST_rts =>            -- request to send
            ps2c_out <= '0';
            tri_c <= '1';
            c_next <= c_reg - 1;
            if(c_reg = 0) then
                Next_State <= ST_start;
            end if;
        when ST_start =>        -- assert start bit
            ps2d_out <= '0';
            tri_d <= '1';
            ps2c_out <= clk20khz;
            tri_c <= '1';
            if (falling_edge(clk20khz)) then
                n_next <= "1000";
                Next_State <= ST_data;
            end if;
        when ST_data =>            -- 8 data + 1 parity
            ps2d_out <= b_reg(0);
            tri_d <= '1';
            ps2c_out <= clk20khz;
            tri_c <= '1';
            if (falling_edge(clk20khz)) then
                b_next <= '0' & b_reg(8 downto 1);
                if n_reg = 0 then
                    Next_State <= ST_stop;
                else
                    n_next <= n_reg - 1;
                    Next_State <= ST_data;
                end if;
            end if;
        when ST_stop =>            -- assume floating high for ps2d
            if (falling_edge(clk20khz)) then
                Next_State <= ST_idle;
                done <= '1';
            end if;
    end case;
    end process;
    
    -- tri_state buffers
    CLOCK_PS_OUT <= ps2c_out when tri_c = '1' else 'Z';
    DATA_PS_OUT <= ps2d_out when tri_d = '1' else 'Z';