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Altera_Forum
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16 years ago

Qurtus vs Modelsim

I wrote code in ModelSim and this code generate wave, who I expected, but Quartus genrate error Error (10822): HDL error at klaw.vhd(110): couldn't implement registers for assignments on this c...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

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Ok, but I use 2 clocks with one clock edges. This isn't synthesizable?

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Do you mean, one signal is assigned depending on two different clock edges? Most likely not synthesizable. You should show a HDL code example for clarification.