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Altera_Forum
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15 years ago

Questions on DQS Mode (Read Clocks, etc) for an SRAM Interface

Hi I’m implementing a DDR2 SRAM interface, which does not seem to have an integrated Altera IP solution like those provided for DDR2 SDRAM or QDR2 SRAM. We’ve tried a few different approaches,...
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Altera_Forum
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15 years ago

I did this about a year ago in Stratix 3. I generated 3 megafunction blocks:

- alt_dq_dqs

- altiobuf_bidir (for the data bidirs)

- altiobuf_in (for dqs and dqsn)

1. The dq_dqs mf block had the DQ_GROUP statements embedded in it (I may have needed to switch between DQ_GROUP 18 and 9 - I'm a tad fuzzy on that recollection).

2. I'm fairly sure it's dedicated routing.

3. CQn should also be on the dedicated routing... in my design, cq/cqn both came through the altiobuf_in cells, then connected to the dqs_input_data_in and dqsn_input_data_in pins of alt_de_dqs. The dqs_bus_out/dqsn_bus_out pins are left unconnected.

I then used an internal clock as a transfer clock, connected ot the dq_ipa_clk pin. I only have some of the info on how I did this, as I'm not at that job anymore, so don't have access to my notebooks.