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Altera_Forum
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15 years ago

Questions on DQS Mode (Read Clocks, etc) for an SRAM Interface

Hi I’m implementing a DDR2 SRAM interface, which does not seem to have an integrated Altera IP solution like those provided for DDR2 SDRAM or QDR2 SRAM. We’ve tried a few different approaches,...
Altera_Forum's avatar
Altera_Forum
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15 years ago

It's been some time now since I wrote a low-level DDR interface and Altera's megacore's have changed somewhat.

Here is what I would recommend.

With the release of Quartus 10.0, Altera has once again made the datapath for their DDR memory controllers open-source. They've labeled this the Uni-phy. So with the 10.0 tools, I would generate a DDR2 SDRAM controller. Look at the generated code and also look at the generated timing SDC constraints. This should give you an idea of how to put together a datapath for your DDR2 SRAM controller.

Jake