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Altera_Forum's avatar
Altera_Forum
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16 years ago

Questions about using LVDS on Stratix III

Hello,

I am using Terasic DE3 board which has Stratix III (EP3SL340H1152C3) on it. The compilation tool I'm using is Quartus II 9.0

I wish to use the HSTC interface to communicate between FPGA's at the maximum bandwidth possible. I started by trying to communicate between the boards at a relatively low frequency and tried various configurations, but all of them failed.

I have several questions regarding LVDS; I am new to LVDS and have started programming FPGA's for three months, so I have little knowledge of LVDS or high speed I/O.

1. What is the (ideal) maximum BW I can get for an interface that has 30 TX pairs of differential signals, 9 of which support true LVDS transmit and 21 are emulated LVDS with termination resistors (LVDS_E_1R) ?

2. According to Stratix III handbook volume 2, table 1-40, the maximum output toggle rate for LVDS_E_1R is 100MHz for class 3, while the single-ended I/O standards show around 300MHz. So, if the data rate is lower for the differential scheme, then why/when should we use LVDS_E_1R?

3. Since I am not familiar with high-speed I/O, I decided to use the ALTLVDS megafunction. Is it correct to use the tx_outclock of the transmitter as the reference input clock (rx_inclock) at the receiver?

4. I started by testing HSTC D interface. The DE3 handbook shows that the clock output pins for HSTC D are at bank 8c (PLL_T1_CLKOUT3, PLL_T1_CLKOUT4 as a differential pair, PLL_T1_CLKOUTn, PLL_T1_CLKOUTp as another pair) . It seems these pins don't support true LVDS transmission, so I chose I/O standard to be LVDS_E_1R. I configured the transmitter to have two channels and deserialization factor of 4, input clock frequency 50MHz, 200Mbps datarate, tx_outclock with divide factor 4. I tried attaching to either of the clocks, but it fails for both cases. The fitter gives an error : "Error: SERDES transmitter

lvds_t:lvds_t_inst|altlvds_tx:altlvds_tx_component|lvds_t_lvds_tx:auto_generated|outclock_tx must drive one output pin". If I try to use one of the data pins for clock output, the fitter compiles okay, but then at the receiver side, since none of the data pins are attached to a dedicated clock input pin, it won't compile. Is there any way to this get around this?

5. Since the error is in the clock output pins, I also tried to using an external PLL. I used the left-right PLL to clock the transmitter, but the rest of the configuration is confusing. What are the clocks that need to be created and what are the frequency and phases supposed to be?

Thank you.

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Although you can expect some help from forum members, it seems necessary, that you read the present documentation more thoroughly. There are some points in your post, that indicate a too casual reading of the device handbook.

    To start with the IO standards. LVDS_E_1R isn't well suited for high speed (although it achieves a data rate of 200 MBPs rather than 100). LVDS_E_3R is the recommended standard for differential outputs without dedicated LVDS driver, allowing 340 upto 550 MBPs, depending on the speed grade.

    It's generally a good idea to use ALTLVDS. I'm not clear about your problems in assigning the PLL output for the reference. I expect, that also Stratix III can use a PLL output. It may be the case, that you are trying to assign a different PLL than used for the LVDS transmitter. The clock outputs aren't dedicated LVDS drivers, but differential and can be used for LVDS with an appropriate IO standard. I admit, that the correct setting isn't always obvious at first sight, although documented in the handbook somewhere.

    It's also not absolutely required to use tx_outclock as reference, the reference clock should be just phase locked to the LVDS transmitter. If you use dynamic phase allignment (DPA) at the receiver, an existing skew of the reference clock would be compensated automaticly.

    External PLL is an option, but requires a better understanding of the involved parameters. I fear, they are not clearly written in a single place in the manuals. You may want to copy the settings from an existing Megafunction compilation. Also a simulation with Altera integrated simulator can be helpful to find out about some features of the LVDS IP.