Questions about using LVDS on Stratix III

Although you can expect some help from forum members, it seems necessary, that you read the present documentation more thoroughly. There are some points in your post, that indicate a too casual reading of the device handbook.

To start with the IO standards. LVDS_E_1R isn't well suited for high speed (although it achieves a data rate of 200 MBPs rather than 100). LVDS_E_3R is the recommended standard for differential outputs without dedicated LVDS driver, allowing 340 upto 550 MBPs, depending on the speed grade.

It's generally a good idea to use ALTLVDS. I'm not clear about your problems in assigning the PLL output for the reference. I expect, that also Stratix III can use a PLL output. It may be the case, that you are trying to assign a different PLL than used for the LVDS transmitter. The clock outputs aren't dedicated LVDS drivers, but differential and can be used for LVDS with an appropriate IO standard. I admit, that the correct setting isn't always obvious at first sight, although documented in the handbook somewhere.

It's also not absolutely required to use tx_outclock as reference, the reference clock should be just phase locked to the LVDS transmitter. If you use dynamic phase allignment (DPA) at the receiver, an existing skew of the reference clock would be compensated automaticly.

External PLL is an option, but requires a better understanding of the involved parameters. I fear, they are not clearly written in a single place in the manuals. You may want to copy the settings from an existing Megafunction compilation. Also a simulation with Altera integrated simulator can be helpful to find out about some features of the LVDS IP.