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Altera_Forum's avatar
Altera_Forum
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10 years ago

Question regarding pulse generation

Hello,

I am a very new user to verilog hdl and unfortunately I don't use it as often so I have to re-learn when I do. I have a simple application where I need to generate a pulse with a duration of 50nS on either the falling edge or rising edge of another signal input and was wondering as to how to approach this in a simple verily statement. Any help would be greatly appreciated. BTW I will be using a 20 or 50 MHz master clock for this device and most likely I will be using a CPLD type device like the MAX3000

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Have you tried to code anything yourself? We're all very happy to help with problems but please have a go first.

    Write code for a counter. Then add a signal decoded from it to generate your pulse...

    Cheers,

    Alex