Question regarding partitions

Thanks for the reply Rysc.

Just one more thing. I also receive warnings regarding the partitions:

-Connecting or removing unused ports

-Avoid driving multiple ports of a partition with the same signal, i.e. the same clock for a rd and wr clk of a DC FIFO

From what I understand, the only disadvantge here is that the design would use up more resouces in the FPGA than it would if the partitions interfaces could be optimized. Please confirm that my thinking on this is ok and that these 900 warnings are really nothing to get alarmed about?

Many thanks for the help