Forum Discussion
Altera_Forum
Honored Contributor
16 years agoI wouldnt rely on or use the Schematic -> HDL converter if I could avoid it. Its not that great, and Ive come across bugs with it, mainly with 2D arrays in schematics being converted to 2d std_logic_vectors (that dont exist as a type). The only time Ive used this feature is when I need to run a simulation on a schematic in modelsim. Then you have the problem of the crappy signal naming for unnamed connections (as you've found).
I would say learn digital design from the schematic, and then try and write your own version of the schematics file. I dont think the auto-generated VHDL is going to teach you alot.