Question on Schematic to VHDL conversion.

I think, most of your questions can be easily answered by trial. Did you notice the option, to name the signals ("wires") in your schematic? You have to use a correct bitwidth for bus signals, however. When you convert the schematic to VHDL afterwards, you'll see, that this is what your asking for. Synthesized_wire_xx signal names are used for unnamed signals only.

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Do I need to create a VHDL file for each page?

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Each schematic is representing a design entity. You can replace no, some or all schematic entities by VHDL design entities in your design, as you like. The design's integrity should be kept anyway.