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Altera_Forum's avatar
Altera_Forum
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11 years ago

Question on return result from a function

Hello,

I am good at Verilog but I have a project where I need to review VHDL so this might be a simple question but I haven't found an answer yet. What does the function below return when n>1?

Thanks,

Chris

function f_sub_clamp(a : std_logic_vector; b : std_logic_vector; constant LEN,n : integer) return std_logic_vector is

variable A_SZ : integer := a'length;

variable B_SZ : integer := b'length;

variable a2 : std_logic_vector(A_SZ-1 downto 0);

variable a0, a1 : std_logic_vector(A_SZ/2-1 downto 0);

variable b2 : std_logic_vector(B_SZ-1 downto 0);

variable b0, b1 : std_logic_vector(B_SZ/2-1 downto 0);

begin

if n>1 then

a2 := a;

a1 := a2(A_SZ-1 downto A_SZ/2);

a0 := a2(A_SZ/2-1 downto 0);

b2 := b;

b1 := b2(B_SZ-1 downto B_SZ/2);

b0 := b2(B_SZ/2-1 downto 0);

return f_sub_clamp(a1, b1, LEN/2, n/2) & f_sub_clamp(a0, b0, LEN/2, n/2);

elsif unsigned(a)>unsigned(b) then

return ext(unsigned(a)-unsigned(b), LEN);

else

return ext("0", LEN);

end if;

end function;

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    This seems like a massively over complicated function. At then end, it appears to just return either a-b, with a load a and b appended to it when a > b or just 0 with a load of a and b appended to it. I really suggest you simulate it to see what it really does.

    It also appears to be non-standard VHDL. given the use of the ext function, I guess it's using the non-standard std_logic_arith library?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    It looks like the "return" is calling the function itself? I guess it is possible because it runs in hardware. I guess I will simulate this to see what it does?