Question on posedge in always block

always @ (posedge asmi_write_n, posedge reset_logic)
begin
if (reset_logic)
flash_addr <= flash_start_add;
else 
begin
if (asmi_write_n)
flash_addr <= flash_addr + 24'h000001;
else
flash_addr = flash_addr;
end
end

According to what has been previously said about Verilog syntax for RTL synthesis, the code doesn't describe synchronous registers. Particularly flash_addr <= flash_addr + 24'h000001 is an asynchronous adder and won't work in synthesis. The question is if asmi_write_n should work as write enable in combination with a system clock or as a clock itself. flash_addr = flash_addr is superfluous in both cases.

asmi_write_n is clock enable

always @ (posedge clk, posedge reset_logic)
begin
if (reset_logic)
  flash_addr <= flash_start_add;
else 
begin
if (asmi_write_n)
  flash_addr <= flash_addr + 24'h000001;
end
end

asmi_write_n is a clock

always @ (posedge asmi_write_n, posedge reset_logic)
begin
if (reset_logic)
  flash_addr <= flash_start_add;
else 
begin
  flash_addr <= flash_addr + 24'h000001;
end
end

Final comment, if flash_start_add isn't a constant but a variable, the asynchronous preset function will be emulated by latches and additional logic because recent FPGA don't have an asynchronous register preset with their core registers. So it would be preferred to use a synchronous preset, if flash_start_add is a variable.