Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

question about wait command in VHDL

Anybody interested in answering a stupid question from a newbee?

Ashenden writes in his book "the Designers guide to VHDL"(second edition page 118) the syntax of the VHDL wait statement is

wait [on signal_name{,...}]

[until boolean_expression]

[for time_expression];

any combination of 3 obtions is allowed.

HOWEVER syntax

quartus2 version 13 NOT accepts

storage: process is

.

.

.

wait on d0;

end process storage;

and DOES accept:

storage: process(d0) is

.

.

.

end process storage;

hence not using the wait statement, but the equivalent semantic

extremely stupid facing icon

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    This is because sensitivity lists are ignored for synthesis, and wait statements are not. A circuit cannot act on a signal'event. The 2nd process will get compiled ignoring the sensitivity list.