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Altera_Forum
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9 years ago

question about wait command in VHDL

Anybody interested in answering a stupid question from a newbee? Ashenden writes in his book "the Designers guide to VHDL"(second edition page 118) the syntax of the VHDL wait statement is ...
Altera_Forum's avatar
Altera_Forum
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9 years ago

This is because sensitivity lists are ignored for synthesis, and wait statements are not. A circuit cannot act on a signal'event. The 2nd process will get compiled ignoring the sensitivity list.