Altera_Forum
Honored Contributor
11 years agoQuestion about Synthesis and fitter
Hi there,
I'm confused about what the Synthesis and Fitter process do. Synthesis converts the HDL codes into gate-level netlist and Fitter is the step which maps the netlist to the LUT or register in the FPGA. Am I right? If so, when I only do synthesis step, why the report also shows the Resources my program cost. Since the netlist have not been mapped to the FPGA,how does the software know the LUT's cost If not, could someone explain these two steps' differences to me? Thanks a lot!