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Aswinkrishnan's avatar
Aswinkrishnan
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
Solved

Questa Simulation

Hi

I am trying to write and read from on-chip memory using SPI in QSYS. The command goes in correctly by observing MOSI line, but the received values are always 0xXX. My question is that

1. In questa, can we view signals of a subcomponent inside a top level component instantiated in the test bench?

2. Is it better to write a test bench on top level entity or on lower level (sub component level)

  • ShengN_altera's avatar
    ShengN_altera
    3 years ago

    Hi,


    Sure. You can view those subcomponent signals by using Wave -> All items in region and below.


    Thanks,

    Best regards,

    Sheng


    p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.


4 Replies

  • ShengN_altera's avatar
    ShengN_altera
    Icon for Super Contributor rankSuper Contributor
    3 years ago

    Hi,


    You may write a test bench on top level entity.

    Then in Questa, go to sim tab -> right-click testbench name -> Add to -> Wave -> All items in region and below


    Thanks,

    Best regards,

    Sheng


    p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.


  • Aswinkrishnan's avatar
    Aswinkrishnan
    Icon for Occasional Contributor rankOccasional Contributor
    3 years ago

    Thank you for the response. I know that. What I meant was, If the top level entity is a qsys component, having a SPI interface and an on-chip memory RAM, can I view the subcomponent signals in my SPI interface. The SPI interface my custom IP consisting of several subcomponents and can I view its signals?

    Like going into submodule level

  • ShengN_altera's avatar
    ShengN_altera
    Icon for Super Contributor rankSuper Contributor
    3 years ago

    Hi,


    Sure. You can view those subcomponent signals by using Wave -> All items in region and below.


    Thanks,

    Best regards,

    Sheng


    p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.


  • Aswinkrishnan's avatar
    Aswinkrishnan
    Icon for Occasional Contributor rankOccasional Contributor
    3 years ago

    Thank you for these quick responses and it helps while learning about the FPGA design as a beginner. Appreciate your help.