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VHDL_User's avatar
VHDL_User
Icon for New Contributor rankNew Contributor
4 years ago

Questa Simulation Not Showing All Needed Variables

I am using Quartus to write my program in and am trying to simulate this in Questa. My program compiles in both applications. When I begin simulation in Questa, some inputs and outputs are missing. They do not appear in the Objects tab where I would be able to pull them over to the simulation tab. Does anyone know where I can find these missing variables to view in simulation? I am using Quartus Prime Pro version 21.3.

13 Replies

  • DrNickels's avatar
    DrNickels
    Icon for Occasional Contributor rankOccasional Contributor

    Ok, I found the QuestaSim manuals. Looks like I'd need to dig into the scripts that Quartus Prime uses to call Questa Intel FPGA Edition to make that happen. That's pretty ugly. And it seems like calling with -O0 (which is a menu option in Questa and generates a warning about slowness of simulation so I know it's being read) would do this.

    Update: in Questa Intel FPGA Edition, you go to Compile/Compile Options, then select the Coverage Tab under "Other Coverage" (the 4th box in 21.1), is an option "Enable Finish State Machine Coverage (+cover f)". If you select that, then hop out of questa and back to quartus and restart questa - yes I'm sure there is a quicker way to do that - then the process in https://nandland.com/view-variables-in-modelsim-waveform/ works - the state, which is a variable, shows up.

    Thanks for the help.

  • KCMurphy's avatar
    KCMurphy
    Icon for Occasional Contributor rankOccasional Contributor

    It's probably a good thing to read msim_setup.tcl and create your own startup call into that, using ld_debug and enum_debug as shown in the verbose output from the setup tcl. But I wouldn't go so far as to modify them directly as they can get recreated by Quartus.

    Here's my normal startup:

    do ../mentor/msim_setup.tcl
    set TOP_LEVEL_NAME testbench_test
    set FORCE_MODELSIM_AE_SELECTION true
    set SILENCE true
    elab_debug -suppress 3016 -t 1ps
    do wave.do
    

    and my rebuild when I create a new IP module in quartus and generate a new script for msim.

    do ../mentor/msim_setup.tcl
    set TOP_LEVEL_NAME testbench_test
    set FORCE_MODELSIM_AE_SELECTION true
    set SILENCE true
    ld_debug -suppress 3016 -t 1ps