Forum Discussion
Questa Simulation Not Showing All Needed Variables
I am using Quartus to write my program in and am trying to simulate this in Questa. My program compiles in both applications. When I begin simulation in Questa, some inputs and outputs are missing. They do not appear in the Objects tab where I would be able to pull them over to the simulation tab. Does anyone know where I can find these missing variables to view in simulation? I am using Quartus Prime Pro version 21.3.
13 Replies
- mistersinha
New Contributor
same query
- SyafieqS
Super Contributor
Miceli,
Is possible to provide sample design and steps that replicate the issue? this could be a bug for Questa since it is recent adopt to Quartus.
- SyafieqS
Super Contributor
Miceli,
May I know if there is any update from my previous query?
- VHDL_User
New Contributor
It ended up being a setting that was automatically turned on for Questa but not for Modelsim. It took me awhile to find because I had never had to change the setting in the past. When simulation is started, there's and optimization setting that must be switched to show full visibility to all variables.
- DrNickels
Occasional Contributor
Could you share what this setting was and how to change it for those coming after with the same problem?
- SyafieqS
Super Contributor
Miceli,
Noted. Seem the issue was resolved let me know if there is any other query at your end otherwise Ill put this to close pending.
- KCMurphy
Occasional Contributor
The issue here is "optimization" which needs to be turned off for logic debug, and probably always in an FPGA design. For verilog, right click on a source, choose "compile properties" and check "use vopt flow" and maybe you want to select an optimization level under coverage. I believe that these settings are project wide. If you need to look into an Altera IP block, you may have to put a comile option into the msim_setup.tcl file. Haven't tied that.
Note: I solved this about a year ago and may be a bit fuzzy on the path.
- DrNickels
Occasional Contributor
Thanks, that gives me a direction to go. I'm using VHDL.
In Questa, I went to "Compile Options" and "Use vopt flow" was already selected. I tried unselecting it (and recompiling and reloading my testbench) with no change. I also tried selecting "Disable optimizations by using -O0" with the same result.
- KCMurphy
Occasional Contributor
Look in the manuals for the vhdl compile command line. In verilog you want the -vopt flag.
- DrNickels
Occasional Contributor
I can't find the "Fine Manual" to read :).
The Help/Questa PDF Bookcase is all dead links. Nothing online seems to have current versions (21.1). vcom does have a -vopt flag, but it doesn't seem to expose variables.
- KCMurphy
Occasional Contributor
It should be in your installation directory
C:\intelFPGA_pro\21.3\questa_fe\docs\pdfdocs\
If you don't have the Intel version, you can download it and get the PDFs