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VHDL_User
New Contributor
New ContributorQuesta Simulation Not Showing All Needed Variables
I am using Quartus to write my program in and am trying to simulate this in Questa. My program compiles in both applications. When I begin simulation in Questa, some inputs and outputs are missing. T...
KCMurphy
Occasional Contributor
Occasional ContributorLook in the manuals for the vhdl compile command line. In verilog you want the -vopt flag.
