Questa Simulation Not Showing All Needed Variables

The issue here is "optimization" which needs to be turned off for logic debug, and probably always in an FPGA design. For verilog, right click on a source, choose "compile properties" and check "use vopt flow" and maybe you want to select an optimization level under coverage. I believe that these settings are project wide. If you need to look into an Altera IP block, you may have to put a comile option into the msim_setup.tcl file. Haven't tied that.

Note: I solved this about a year ago and may be a bit fuzzy on the path.