Questa not showing signals from verilog models
Hello.
I've just started using intel Questasim vs intel modelsim and it is faster! Which is great! Time to regress on my laptop went from around 37 minutes to around 25 minutes.
However, my regressions had a single test failure (actually a single bit failure). So I need to run a simulation with waveforms to see what is going on and fix the testbench (probably).
I already have a .do file for simulating this test, but none of the signals it refers to are found when it tries to load.
And when I traverse the design tree in questa, none of my verilog modules show any signals at all. Many of the modules are completely free of Objects.
Yet the simulation runs and, except for the one issue I need to debug, completely works!
I'm running Questa on linux.
Any help would be appreciated.