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BrianM's avatar
BrianM
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Questa not showing signals from verilog models

Hello. I've just started using intel Questasim vs intel modelsim and it is faster! Which is great! Time to regress on my laptop went from around 37 minutes to around 25 minutes. However, my reg...
BrianM's avatar
BrianM
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

For anyone who finds this thread in the future. The fix is to enable access in vlog and in vsim and suppress the error message like this:

From msim_setup.tcl:

if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] {
set USER_DEFINED_VERILOG_COMPILE_OPTIONS "+acc -suppress 12110"
}
if ![info exists USER_DEFINED_ELAB_OPTIONS] {
set USER_DEFINED_ELAB_OPTIONS "+acc -suppress 12110"
}