Forum Discussion
Hi Everyone,
as i can tell you first that questa was opening up and i can compile the design code and stimulate with waveform.
but, this case i was addding up UVM testbench files . so compile was coming clean but in time of simulation. i was facing issue
# Loading C:/intelFPGA_lite/23.1std/questa_fse/uvm-1.1d\win64\uvm_dpi.dll
# ** Error: Failure to checkout svverification license feature.
Error: (vsim-1) Unable to checkout verification license - required for testbench features (randomize, randcase, randsequence, covergroup).
# Time: 0 ps Iteration: 0 Instance: /tb_top File: C:/../BKansagara/../Work Data Slot/Questa_PROJECT_ALU/testsv/tb_top.sv
I had done like :
1) i had installed software and I only got the license.dat file to activate Quartus Prime and Questa,
2) I set an environment variable pointing to that file.
3) i can do compile clean for design and top testbench module of uvm.
4) simulation with this Error (waiting here to come in conclusion)
as, I had searched in internet, so I got result for this issue on :
Error: Failure to checkout svverification license feature.
Fatal: (vsim-7099) Unable to check out a verification license for the randomize() feature.
Comment on this error (internet): As far as I was able to understand, that's one of the limitations of Starter Edition. is it so?
I am sharing the screenshot as well. can anyone please help me on the same?
Thanks,
Bansari