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jeffrs20
New Contributor
New ContributorQuesta doesn't show UUT under Work
This is for Quartus Prime Standard and Questa Sim (both licensed). Under the test bench, the instantiated UUT should be present. As I'm a novice I puzzled over what I was doing wrong. However, I s...
When you generate a simulation script for an IP or an example design, it does.
sstrell
Super Contributor
Super ContributorAny screenshots? Code? Hard to figure out what's going on here without seeing anything you've done.
jeffrs20New Contributor
New ContributorHello. This is the simple tutorial source file. This compiles without issues. Attached is a screenshot of the Questa RTL sim, showing the testbench, but no DUT.
Thank you.
module fullAdder (A,B,cin,sum,cout);
input A,B,cin;
output sum, cout;
assign sum = A ^ B ^ cin;
assign cout = A & B | cin & (A ^ B);
endmodule
module fullAdder_testbench();
reg A,B,cin;
wire sum, cout;
fullAdder dut (A, B, cin, sum, cout);
initial begin
A = 0; B = 0; cin = 0; #10;
cin = 1; #10;
B = 1; cin = 0; #10;
cin = 1; #10;
A = 1; B = 0; cin = 0; #10;
cin = 1; #10;
B = 1; cin = 0; #10;
cin = 1; #10;
$stop;
end //initial
endmodule
