quartus/verilog short-circuit operator

Hi,

I have this code which other synthesis and simulation tools like, but quartus does not. It looks something like:

reg [7:0] something;

integer i;

always @(*) begin

for (i = 0 ; i <8 ; i = i + 1) begin

if ((i==0) || ((i >= 1) && something[i-1]) || ((i >= 2) && something[i-2])) begin

.....

quartus thinks we're trying to evaluate something[-1] but I think not.

I'm not totally sure about verilog rules on short-circuit'ing

What do you think ?

Thanks