Altera_ForumHonored Contributor15 years agoQuartusII verilog compiler hangs consuming 100% cpu Hello, all! I'm trying to create memory cache controller in Verilog from scratch. I'm using QuartusII 10.0 Web Edition under Linux. Cache controller consists from 2 memory modules (based on the ...Show Moresora-fail1.tar.gz37 KB
Altera_ForumHonored Contributor15 years agoSR is a "Service Request" but I don't know how to file one.
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