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Altera_Forum's avatar
Altera_Forum
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15 years ago

QuartusII verilog compiler hangs consuming 100% cpu

Hello, all! I'm trying to create memory cache controller in Verilog from scratch. I'm using QuartusII 10.0 Web Edition under Linux. Cache controller consists from 2 memory modules (based on the ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I'm sorry, I'm a beginner in FPGA design and English is not my native language.

As far as I understand your message, this problem appears on your computer too, right? And can your explain, what is 'SR' and where I should send it?

Many thanks for your response.

Best regards, Alexander.