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Altera_Forum's avatar
Altera_Forum
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16 years ago

QuartusII Fitter problem

Hi, I am compiling a counter source code but the compilation get stuck at the beginning of Fitter, it is running and seems will never stop...:confused:

The following info were shown:

Info: *******************************************************************

Info: Running Quartus II Fitter

Info: Version 7.2 Build 151 09/26/2007 SJ Web Edition

Info: Processing started: Wed Sep 23 17:28:42 2009

Info: Command: quartus_fit --read_settings_files=on --write_settings_files=off counter_test -c counter_test

Info: Selected device EP2C20F484C7 for design "counter_test"

Warning: The high junction temperature operating condition is not set. Assuming a default value of '85'.

Warning: The low junction temperature operating condition is not set. Assuming a default value of '0'.

Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time

Warning: Feature LogicLock incremental compilation is not available with your current license

Info: Fitter is using the Classic Timing Analyzer

Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.

I've seen those warnings befroe and they doesn't matter seriously.

I attach my code here. Hope someone could help me here, give me a clue what is going on??:confused:

7 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I can see some progress now...but still it is running quite slowly, this doesn't make sense.There are more than one thousand iterations but it takes 20 minutes to run 13%.

    Has someone have similar situation before?
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Well I'm compiling it now in 9.0. I have a very fast machine. It's been running for 24 minutes and it's at 71% on the fitter. I don't speak VHDL very well so it'll take me a minute to figure this out but the synthesis reported:

    --- Quote Start ---

    Warning: Design contains 1 input pin(s) that do not drive logic

    Warning (15610): No output dependent on input pin "CLOCK"

    --- Quote End ---

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Many thanks, it works much more faster now~ Looks like the for loop helps alot. Could you explain me why?

    BTW, there's no output dependent on CLOCK now, because now I'm testing the counter's function, later I will need to change clock frequency to make it count every second.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    @changjianchun,

    What you have written is in VHDL is in your process is a cascade of 1024 incrementers of which the output is connected to the display. This is one huge block of combinatorial logic. This takes a lot of gates and also a lot of Logic Elements in your FPGA. The propagation delay will also be very large.

    The addition of the 

    if(CLOCK'event and CLOCK = '1') then

    does not change this.

    The logic that you have developed is too slow for the 50MHz clock that you are using on your DE2 board.

    The effect of the "for" loop in your application is only replicating hardware to be generated. So you should remove that.

    Running this example on 50 MHz will count your 16bit counter still much too fast. You could extend it to 32 bits and also include further 7 segment displays HEX4...HEX7 .

    Your "procedure" display should better be defined as a hardware module. You better define an entity and architecture display.

    Hope this helps...
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    @changjianchun,

    here is an update of what you probably intended your VHDL description to do. The counter cnt has been extended to 32 bits and 4 more HEX displays are added. In case your board has only 4, you should use the 16 most significant bits of the cnt counter to display, as you will otherwise not see anything. 

    library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity display is
  port (
  c: in std_logic_vector (3 downto 0);
  HEX: out std_logic_vector (6 downto 0)
  );
end entity display;
architecture logic of display is
begin    
    process (c)
    begin
  case c is
 
  when X"0" =>
   HEX <= "1000000";
  when X"1" =>
   HEX <= "1111001";
  when X"2" =>
   HEX <= "0100100";
  when X"3" =>
   HEX <= "0110000";
  when X"4" =>
   HEX <= "0011001";
  when X"5" =>
   HEX <= "0010010";
  when X"6" =>
   HEX <= "0000010";
  when X"7" =>
   HEX <= "1111000";
  when X"8" =>
   HEX <= "0000000";
  when X"9" =>
   HEX <= "0010000";
  when X"a" =>
   HEX <= "0001000";
  when X"b" =>
   HEX <= "0000011";
  when X"c" =>
   HEX <= "1000110";
  when X"d" =>
   HEX <= "0100001";
  when X"e" =>
   HEX <= "0000110";
  when X"f" =>
   HEX <= "0001110";
  end case;
    end process;  
end architecture; 
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity counter_test is
  port (
 CLOCK_50: in std_logic;
 KEY: in std_logic_vector (3 downto 0);
 HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7: out std_logic_vector (6 downto 0)
 );
end entity counter_test;
 
architecture behav of counter_test is
 
 component display is
   port (c: in std_logic_vector (3 downto 0);
      HEX: out std_logic_vector (6 downto 0));
    end component;
 
 signal cnt: std_logic_vector (31 downto 0);
 signal c0,c1,c2,c3,c4,c5,c6,c7 : std_logic_vector (3 downto 0);
 signal a,b,c,d,e,f,n,m:std_logic_vector (6 downto 0);
 signal reset_n : std_logic;
 signal CLOCK : std_logic;
 
 begin 
 
 reset_n <= KEY(0);
 clock <= CLOCK_50;
 
    d0: display port map(c0,a); 
 d1: display port map(c1,b); 
 d2: display port map(c2,n); 
 d3: display port map(c3,m); 
 d4: display port map(c4,c);
 d5: display port map(c5,d);
 d6: display port map(c6,e);
 d7: display port map(c7,f);
 
 c0 <= cnt (3 downto 0); 
 c1 <= cnt (7 downto 4);
 c2 <= cnt (11 downto 8);
 c3 <= cnt (15 downto 12);
 c4 <= cnt (19 downto 16);
 c5 <= cnt (23 downto 20);
 c6 <= cnt (27 downto 24);
 c7 <= cnt (31 downto 28);
 HEX0<= a;
 HEX1<= b;
 HEX2<= n;
 HEX3<= m;
 HEX4<= c;
 HEX5<= d;
 HEX6<= e;
 HEX7<= f;
 
  process 
  begin  
            wait until (CLOCK'event and CLOCK = '1');
              if (reset_n = '0') then
                    cnt <= X"00000000";
              else 
        cnt <= cnt + 1;  
     end if;
  end process; 
 
end architecture behav;

    You can notice that several things have been changed with respect to your original description.

    I advise you to read a good book on VHDL design. I can suggest you the book of peter ashenden (http://www.ashenden.com.au/) "The Designer's Guide to VHDL".

    Hope this helps...
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Hi, I changed my code according to your suggestion, but still I cannot see counter counting on the display segments (tbw, I have only 4 digits). I think that's because I didn't introduce a clock properly from the device to the FPGA chip.There are some internal clock frequency inside the device? Do you have any idea about this?