QuartusII Fitter problem

@changjianchun,

What you have written is in VHDL is in your process is a cascade of 1024 incrementers of which the output is connected to the display. This is one huge block of combinatorial logic. This takes a lot of gates and also a lot of Logic Elements in your FPGA. The propagation delay will also be very large.

The addition of the

if(CLOCK'event and CLOCK = '1') then

does not change this.

The logic that you have developed is too slow for the 50MHz clock that you are using on your DE2 board.

The effect of the "for" loop in your application is only replicating hardware to be generated. So you should remove that.

Running this example on 50 MHz will count your 16bit counter still much too fast. You could extend it to 32 bits and also include further 7 segment displays HEX4...HEX7 .

Your "procedure" display should better be defined as a hardware module. You better define an entity and architecture display.

Hope this helps...